Learn RADARs and FPGA on Practice

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Learn RADARs and FPGA on Practice

Embedded Systems Optimization

AXI DMA with HLS

Acceleration with FPGA

Fast Fourier Transform

Cell-Averaging CFAR

Ordered-Statistic CFAR

Direct Digital Synthesizer

Deep Learning with ZU+ MPSoC

Vivado Hardware Design for Deep Learning Unit

Linux Deployment for Vitis AI enviroment

Vitis AI Library Examples

Learn RADARs and FPGA on Practice

Embedded Systems Optimization

AXI DMA with HLS

Acceleration with FPGA

Fast Fourier Transform

Cell-Averaging CFAR

Ordered-Statistic CFAR

Direct Digital Synthesizer

Deep Learning with ZU+ MPSoC

Vivado Hardware Design for Deep Learning Unit

Linux Deployment for Vitis AI enviroment

Vitis AI Library Examples

Folder: Embedded Systems Optimization

AXI DMA with HLS

Folder: Acceleration with FPGA

Fast Fourier Transform

Cell-Averaging CFAR

Ordered-Statistic CFAR

Direct Digital Synthesizer

Folder: Deep Learning with ZU+ MPSoC

Vivado Hardware Design for Deep Learning Unit

Linux Deployment for Vitis AI enviroment

Vitis AI Library Examples

Lessons, Workshops for FPGA, System On Chip, Digital Signal Processing in RADAR based systems

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