Features of the lesson package (paid content)

   ➢   Fully pipelined HLS implementation of DDS IP core (LookUp method) based on DATAFLOW optimization

  ➢   Vitis HLS 2022.2 DDS IP core Implementation, Co-simulation and performance analysis

   ➢   AXI STREAM interfaces for input phase of desirable digital waveform and complex output

➢ Optional phase dithering and Taylor series correction implementation to increase spurious free dynamic range

➢ Synthesizable pseudo number linear congruential generator implementation for phase dithering

➢ Example of the Hardware Design in Vivado 2022.2 with HLS DDS IP core for Arty Z7-20 board with verification in Python