Direct Digital Synthesizer Vitis HLS Implementation
Features of the lesson package (paid content)
➢ Development of fully pipelined DDS IP cores in Vitis HLS
➢ Phase truncated, dithered and Taylor serial output corrected options
➢ Integration and configuration the Xilinx AXI DMA and AXIS SWITCH IP cores
➢ DDS IP core Spurious Free Dynamic Range estimation
➢ Linux Deployment for Zynq-7000 (Arty z7-20) with Buildroot
The Synthesis Report for 8192 input samples
Architecture for HLS DDS IP core
Vivado Hardware Design for Arty z7-20
The Educational Packages Sources