CFAR detector Vitis HLS Implementation
Features of the lesson package (paid content)
➢ Fully pipelined, run-time configurable Cell-Averaging and Ordered-Statistic CFAR IP cores in Vitis HLS
➢ Integration and run-time configuration of the Xilinx AXI DMA and AXIS SWITCH IP cores under Linux
➢ Fixed-point input signal simulation and CFAR IP cores performance estimation
➢ Linux deployment for Zynq 7000 SoCs with Buildroot for dynamic FPGA reconfiguration and Vitis HLS IP cores support
➢ Tested with Arty z7-20 board
The Educational Package sources
Vivado Hardware design for Arty z7-20
CFAR IP cores detection results
Synthesis and Implementation report 1024 samples for Arty z7-20