Matched Filter Vitis HLS Implementation
Architecture of MF IP core Vitis HLS implementation in frequency domain
Features of the lesson package (paid content)
➢ Implementation of fully pipelined Matched Filter IP cores in Vitis HLS
➢ Time and frequency domain implementation
➢ Handling the Xilinx AXI DMA and AXIS SWITCH IP cores
➢ Matched Filter: Time vs Frequency performance estimation
➢ Linux Deployment for Zynq-7000 with Buildroot
Vivado Hardware design for Arty z7-20
The Educational Package sources
Matched Filter IP core input and output: in time and frequency domain
Synthesis and Implementation report for 1024 input samples
Time vs Frequency domain: DSP blocks usage