Matched Filter Vitis HLS Implementation

Fully pipelined, run time configurable, axi interface compliant
Matched Filter IP core Vitis HLS Implementation

Features of the lesson package (paid content)

   ➢   Matched Filter in frequency domain IP core microarchitecture for HLS and Python modeling for verification for fixed-point arithmetic

   ➢   AXI STREAM interfaces for complex input / output and coefficients samples, AXI lite for run time configuration of FFT cascades scaling schedule

➢   Vitis HLS 2022.2 MF IP core Implementation, Co-simulation and performance analysis

➢ Vivado 2022.2 Hardware Design with HLS MF IP core, Scatter-Gather AXI DMA and Zynq 7000 Processing System

➢ Example of C Standalone Application with C-drivers for HLS MF IP core with Scatter-Gather AXI DMA on Arty Z7-20 board

Detailed explanation of Vitis HLS Matched Filter IP core imlementation

Implementation Report for 512 complex samples