Features of the lesson package (paid content)

   ➢  FFT IP core microarchitecture for HLS and Python modeling for verification

➢  AXI STREAM interfaces for complex input / output samples

   ➢   Vitis 2022.2 HLS FFT IP core Implementation, Co-simulation and performance analysis

   ➢  Vivado 2022.2 Hardware Design with HLS FFT IP core, AXI DMA and Zynq 7000 Processing System

   ➢   Example of C Standalone Application with C-drivers for AXI DMA and HLS FFT IP core verification on Arty Z7-20 board