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Learn RADARs and FPGA on Practice

Mastering Xilinx DSP IP cores

Acceleration with FPGA

AXI DMA with HLS

Fast Fourier Transform

Direct Digital Synthesizer

Deep Learning with ZU+ MPSoC

Vivado Hardware Design for Deep Learning Unit

Linux Deployment for Vitis AI enviroment

Vitis AI Library Examples

Object Detection with OFA-YOLO

Learn RADARs and FPGA on Practice

Mastering Xilinx DSP IP cores

Acceleration with FPGA

AXI DMA with HLS

Fast Fourier Transform

Direct Digital Synthesizer

Deep Learning with ZU+ MPSoC

Vivado Hardware Design for Deep Learning Unit

Linux Deployment for Vitis AI enviroment

Vitis AI Library Examples

Object Detection with OFA-YOLO

Folder: Udemy Courses

Mastering Xilinx DSP IP cores

Folder: Acceleration with FPGA

AXI DMA with HLS

Fast Fourier Transform

Direct Digital Synthesizer

Folder: Deep Learning with ZU+ MPSoC

Vivado Hardware Design for Deep Learning Unit

Linux Deployment for Vitis AI enviroment

Vitis AI Library Examples

Object Detection with OFA-YOLO

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