Digital Signal Processing on Zynq 7000 SoC for Jamming Systems

Agenda:

  1. Course Introduction

  2. IQ demodulator: NCO – numerically controlled oscillator

  3. IQ demodulator: FIR FILTER – hardware design and implementation

  4. IQ demodulator and decimation (HDL design)

  5. Vivado High Level Synthesis Tutorial

  6. IQ modulator and Interpolator(HDL design)

  7. Frequency and Phase modulation (HDL design)

  8. Vivado HLS: up/down converters, IQ frequency and phase modulation

  9. Zynq 7000: Overview, GPIOs, Interrupt Controller

  10. Zynq 7000: AXI DMA in Direct Register Mode

  11. Zynq 7000: AXI DMA in Scatter Gather Mode

  12. Zynq 7000: Lightweight IP, FSBL

  13. Zynq 7000: AXI DMA Networking

  14. Zynq 7000: Analog Devices FMCOMMS1 module integration

  15. Zynq 7000: digital signal processing with FMCOMMS1 module

  16. Zynq 7000: Linux start guide, AXI GPIO example

Boards: ZED board, ZC702, ZC706 with EVAL-AD4080-FMCZ mezzanine card

Digital Signal Processing on Zynq 7000 SoC for Range-Doppler RADAR Systems

Agenda:

  1. UDP/IP server/client implementation for Baremetal Zynq 7000

  2. AXI DMA controller for Range-Doppler Processing Chain

  3. Vitis HLS: Hardware Design and implementation of real time configurable Matched Filter in frequency domain for Zynq 7000

  4. Range-Doppler Matrix Transpose with multithreading 

  5. Vitis HLS: Hardware Design and implementatio of FFT for Zynq 7000

  6. Vitis HLS: Hardware Design and implementation of Real time configurable Ordered Statistic 1D CFAR

  7. Vivado Hardware Design for Signal Processing chain: ADC - Matched Filter - Doppler FFT - OS CFAR - UDP

  8. Software architecture (Standalone, Linux) for Signal Processing Chain: ADC - Matched Filter - Doppler FFT - OS CFAR - UDP

Boards: ZED board, ZC702, ZC706