Fully pipelined, run time configurable, axi interface compliant,
Cell-Averaging CFAR IP core Vitis HLS Implementation

Cell-Averaging CFAR Vitis HLS Implementation

Features of the lesson package (paid content)

➢ CA CFAR IP core microarchitecture for HLS and Python modeling for verification

➢ Vitis HLS 2022.2 CACFAR IP core Implementation, Co-simulation and performance analysis

➢ Vivado 2022.2 Hardware Design with HLS CACFAR IP core, AXI DMA and Zynq 7000 Processing System

➢ Example of C Standalone Application with C-drivers and Run Time Configuration for HLS CACFAR IP core with AXI DMA on Arty Z7-20 board

➢ AXI STREAM slave interface for complex samples, AXI STREAM master interface for CFAR decision and AXI Lite for HLS CACFAR IP adjustment

Detailed explanation of Vitis HLS CA CFAR IP core imlementation

Implementation Report for 1024 complex samples input and 14 reference cells