AXI DMA with HLS

Processing System (PS) - Programmable Logic (PL) data transfer with Vitis High-Level Synthesis by using AXI Memory Mapped and STREAM interfaces

Features of the lesson package (paid content)

   ➢  Hardware design for PS-PL data transfer with Vitis HLS 2022.2

  ➢  Embedded Linux Deployment with Buildroot out-of-tree configuration

   ➢  Dynamic reconfiguration and device tree overlay with FPGA Manager Framework

➢ Open Asymmetric Multi-Processing Framework (Open AMP) example for Cortex R5

➢ AXI DMA HLS IP core C drivers usage example for standalone, Linux C and Python applications

➢ Python Linux application with Simplified Wrapper and Interface Generator (SWIG)

Data Transfer between Processing System and Programmable Logic for Zynq/ZynqUS+ SOC by using Vitis HLS