Fully pipelined, run time configurable, axi interface compliant,
Ordered-Statistic CFAR IP core Vitis HLS Implementation
Ordered-Statistic CFAR Vitis HLS Implementation
Features of the lesson package (paid content)
➢ OS CFAR IP core microarchitecture for HLS and Python modeling for verification
➢ Vitis HLS 2022.2 OS CFAR IP core Implementation, Co-Simulation and performance analysis
➢ Vivado 2022.2 Hardware Design with HLS OS CFAR IP core, AXI DMA and Zynq 7000 Processing System
➢ Example of C Standalone Application with C-drivers and Run Time Configuration for HLS OS CFAR IP core with AXI DMA on Arty Z7-20 board
➢ AXI STREAM slave interface for complex samples, AXI STREAM master interface for CFAR decision and AXI Lite for HLS OS CFAR IP adjustment
Implementation Report for 2048 samples input and 16 reference cells
